My Profession

    By profession, I am a Senior Design Engineer in the field of Analog and Mixed Signal design. Currently I'm employed at Sankalp Semiconductor Pvt. Ltd, a global mixed signal semiconductor service and solution provider.

    At Sankalp Semiconductor I am responsible for circuit design of high speed clock generators and synthesizers using CAD tools on LINUX platform. But my job is not restricted only to circuit design, I am involved every phase of VLSI design cycle ranging from specification derivation,behavioral modeling, circuit design, simulation, circuit layout, post layout extracted view simulation, CAD tool evaluation, in-house CAD tool development and automation to reduce cycle time etc. Apart from this, I am involved in training of new assets in Sankalp Semiconductor.

    I have started my professional career with Sankalp Semiconductor Pvt. Ltd (India) and working here since 2008. In the initial phase of my carrier, I worked on layout of various modules. Later in 2009, I joined the Sankalp Analog Solution (SAS) division and started my carrier as a circuit designer. I am mainly working in the design and layout of modules in 65nm and 45nm CMOS technologies.

    Worked on multiple CPUMP PLLs from different Technologies and difference architecture. Wide Input range, V2I splitter, FLL based PLL, Free Running VCO Type, Programmable, SSCG Type, Fractional etc.

    Apart from technical know hows, I had organized Sankalp@5 for Sankalp East Division. I have remained part of the core organizing team of Sankalp@6 and Sankalp@7. By the way, Sankalp@5 means 5th annual day celebration of Sankalp Semiconductor. I have learn a lot on people management, working with vendors, budgeting of the expenditures and many more. I am part of the site event team, that organizes multiple events for assets round the year.

    Worked on development of a wrapper for Power EM analysis. The wrapper includes Assura LVS check, Assura QRC (RCX) resistor extraction, Extracted view simulation and VPS EM analysis tools.In most of the cases, the code generates the required schematic test-bench to reduce verification time.

    Generally, in analog designs, we have to design amplifiers with different specifications many a time. I have also worked on to automate amplifier design flow, so that from the device characterization results of a particular technology and few input parameters, the required amplifier can be designed with minimal simulation requirement and minimal designer intervention. The final result of the automation will be a design in a schematic view. Though I have not done the automation fully myself, I have set the standard of the automation flow.

Present Work:

    At present, I am working as a contractor to Texas Instruments India (TII). My responsibilities include final sign-off of the Test-Chip schematic along with Test-Chip level verification. My current Test-Chip includes different type of IPs, like Power Management, ADC, Area optimized IOs, Video Transmitters etc.

Technical Skills:

  • Modeling / Programming Language: C, C++, VHDL, Verilog, Verilog-A, Skill, Perl, Python, Shell
  • Operating System: Windows XP, Red-Hat LINUX
  • Technology: Sub-micron CMOS technologies
  • Tool Expertise : Virtuoso Schematic, Layout, Layout XL Editor, ADE-L, ADE-XL, Spectre, Ocean, Assura Verification Flow(DRC/LVS/RCX), Hercules Verification flow (DRC/LVS), Laker ADP, Laker L2/L3, Tanner EDA : S-edit, L-edit, T-spice, W-edit, Mentor Graphics ICSTUDIO.
  • Area of Expertise: PLL, VCO, Frequency Dividers, Precision Sine Oscillators, Amplifiers


  • Nominated as Divisional Innovation Champion for the month of December 2009 and automation champion in April 2012.
  • Participated in Sankalp Technical Conference (STC) 2011 and presented on the topic "A novel bias scheme for wide range CMOS VCO."
  • Paper in STC-2012 on "A Precision Sine Wave Oscillator with Excellent Amplitude and Frequency Stability and Low Distortion"
  • Paper on "A wide range CMOS VCO for PLL applications", submitted in 26th International Conference on VLSI Design 2013. IEEE Link : A wide range CMOS VCO for PLL applications

Note:- Detailed description on my professional carrier is given in my CV.

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